`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/24 08:46:58
// Design Name: HW5
// Module Name: motor_FSM
// Project Name: hw5
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: Homework 5 for Fudan PLD & HDL courses
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module motor_FSM(
    input clk,              //时钟
    input dir,              //dir规定了马达转向，dir=0时马达向前forward，dir=1时马达向后backward
    input rst_n,            //复位信号rst_n            
    output reg [3:0] A      //输出电机控制信号
    );
    
    //显示状态机
    reg [3:0]state;         //记录状态机的状态
    always @(posedge clk or negedge rst_n) begin
        if(rst_n) begin          //rst复位重置clk, A, state
            A <= 4'b0000;
            state <= 4'b0000;
        end
        else begin
            case (state)
                4'b0000: begin
                    A <= 4'b0001;         // A
                    if(dir) 
                        state <= 4'b0111;
                    else
                        state <= 4'b0001;
                end
                4'b0001: begin
                    A <= 4'b0011;         // AB
                    if(dir) 
                        state <= 4'b0000;
                    else
                        state <= 4'b0010;
                end
                4'b0010: begin
                    A <= 4'b0010;         // B
                    if(dir) 
                        state <= 4'b0001;
                    else
                        state <= 4'b0011;
                end
                4'b0011: begin
                    A <= 4'b0110;         // BC
                    if(dir) 
                        state <= 4'b0010;
                    else
                        state <= 4'b0100;
                end
                4'b0100: begin
                    A <= 4'b0100;         // C
                    if(dir) 
                        state <= 4'b0011;
                    else
                        state <= 4'b0101;
                end
                4'b0101: begin
                    A <= 4'b1100;         // CD
                    if(dir) 
                        state <= 4'b0100;
                    else
                        state <= 4'b0110;
                end
                4'b0110: begin
                    A <= 4'b1000;         // D
                    if(dir) 
                        state <= 4'b0101;
                    else
                        state <= 4'b0111;
                end
                4'b0111: begin
                    A <= 4'b1001;         // DA
                    if(dir) 
                        state <= 4'b0110;
                    else
                        state <= 4'b0000;
                end
                default: begin            // default
                    A <= 4'b0000;
                    state <= 4'b0000;
                end
            endcase
        end
    end
endmodule
